Method to prevent corrosion of bond pad structure

ABSTRACT

There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuitfabrication methods and particularly, to fabrication methods thatmitigate the problem of bond pad corrosion.

BACKGROUND OF THE INVENTION

Integrated circuits are used in many portable electronic products, suchas cell phones, portable computers, voice recorders, etc. as well as inmany larger electronic systems, such as cars, planes, industrial controlsystems, etc. Integrated circuits may include a combination of activedevices, passive devices and their interconnections. In order toelectrically connect the integrated circuit components to a pointexternal of it, bond pad structures are provided.

The schematic cross-section of FIG. 1 illustrates a known integratedcircuit system 100 comprising a substrate 101 having a top metal layer112 embedded within an interlayer dielectric 110. Attached to a lowersurface of the top metal layer 112 is a via 114 which may be connectedto an underlying metal layer or circuit components (not shown). A bondpad 120 is formed at an upper surface of the top metal layer 112. Thebond pad is conductive and may comprise metals such as aluminum-basedalloys (such as Al—Cu or Al—Cu—Si). A passivation layer 140 is formedover the interlayer dielectric 110 and the bond pad 120, with an openingcreated in the passivation layer 140 so that an upper surface portion ofthe bond pad 120 is exposed. As illustrated in FIG. 1, a ball bond 160is formed in contact with the exposed portion of the bond pad. The ballbond 160 has a wire bond 162 attached thereto for connecting the bondpad 120 and hence integrated circuit to a location external of it. Thelocation external of the integrated circuit may include packaging leads,a circuit board or another integrated circuit.

A problem often encountered in the fabrication of integrated circuits isbond pad corrosion which is the depletion of materials used in the bondpad. This phenomenon is undesirable because it results in the formationof pits or pinholes at the upper surface of the bond pad which canaffect the adhesion reliability of subsequent bonding contacts such asball bonds to the bond pad. Therefore, fabrication processes that canmitigate the problem of bond pad corrosion are desirable.

SUMMARY OF THE INVENTION

The present invention relates generally to methods for fabricatingintegrated circuits and in particular, to methods for preventing thecorrosion of bond pads.

In accordance with one aspect of the invention, there is provided amethod for fabricating an integrated circuit comprising providing asubstrate with a bond pad formed thereover, the bond pad having a topsurface for the formation of bonding connections. A passivation layer isprovided over the bond pad followed by the formation of a masking layerover the passivation layer. The passivation layer is subsequently etchedin accordance with the masking layer to form a patterned passivationlayer with an opening that exposes a portion of the top surface of thebond pad. After etching the passivation layer, the masking layer isremoved and a bond pad protective layer is subsequently formed on theexposed top surface portion of the bond pad.

These and other objects, along with advantages and features of thepresent invention herein disclosed, will become apparent throughreference to the following description and the accompanying drawings.Furthermore, it is understood that the features of the variousembodiments described herein are not mutually exclusive and can exist invarious combinations and permutations.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference numbers generally refer to the sameparts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention. In the followingdescription, embodiments of the invention will now be described, by wayof example with reference to the drawings of which

FIG. 1 is a schematic cross-sectional view of a known integrated circuitsystem comprising a bond pad structure;

FIGS. 2 to 5 are schematic cross-sectional views illustrating theresults of progressive stages in fabricating an integrated circuitsystem in accordance with one embodiment of the invention; and

FIG. 6 is a schematic cross-sectional view illustrating an integratedcircuit system in accordance with another embodiment of the invention.

DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to theattached figures, wherein like reference numerals are used to refer tolike elements throughout.

FIGS. 2-5 are cross-sectional views illustrating by way of example andnot by limitation, an exemplary process flow for the formation of anintegrated circuit system 200 according to an embodiment of the presentinvention. It is to be understood that a plurality of conventionalprocesses that are well known in the art and not repeated herein, mayprecede or follow FIGS. 2-5.

Referring now to FIG. 2, therein is shown a partial cross sectional viewof an integrated circuit system 200 in an intermediate stage ofmanufacture. The integrated circuit system comprises a substrate 201having a top metal layer 212 embedded within an interlayer dielectric210. Although not illustrated in FIG. 2, the substrate typically alsocomprises a plurality of active and passive devices formed below the topmetal layer 212 and interconnect structures linking some of the devicesto the top metal layer 212. The interconnect structures typicallycomprise metallic traces and vias embedded in one or more layers ofdielectric material. Attached to a lower surface of the top metal layer212 is a via 214 which may be connected to an underlying interconnect orcircuit components (not shown).

A first dielectric layer 220 is provided over the interlayer dielectric210 and top metal layer 212. In one embodiment, the first dielectriclayer 220 comprises silicon oxide. Alternatively, other dielectriclayers such as TEOS may also be suitable. An opening is created throughthe first dielectric layer 220 and filled with a bond pad 260 the bottomsurface of which contacts a top surface of the top metal layer 212. Asshown in FIG. 2, the top surface of the bond pad 260 is situated abovethe height of the first dielectric layer 220. The bond pad electricallyconductive in nature and may comprise metals or alloys thereof such asAluminum copper or aluminum silicon copper. Alternatively, otherconductive materials may also be used and the bond pad may also be alaminate structure made up of additional layers of material such ascopper, titanium, titanium nitride or combinations thereof.

A passivation layer 280 is formed over the bond pad 260 and firstdielectric layer 220 such that the bond pad is embedded in thepassivation layer 280. The passivation layer 280 protects underlyingcomponents of the integrated system 200 from external contaminants suchas moisture and mechanical damage. In one embodiment, the passivationlayer 280 comprises silicon nitride. Alternatively, other materials suchas silicon oxynitride and polyimide may also be used as a passivationlayer in addition to or in place of silicon nitride.

A photoresist layer is deposited on the entire surface of thepassivation layer 280 and selectively exposed and developed to form amasking layer 290 for patterning the passivation layer. As shown in FIG.2 the masking layer 290 includes an opening situated at a locationoverlying the top surface of the bond pad 260.

FIG. 3 shows the semiconductor system 200 of FIG. 2 after thepassivation layer 280 has been etched in accordance with the maskinglayer 290 by a reactive ion etching (RIE) process. The masking layer 290prevents passivation layer regions underlying it from being etched whileexposed portions of the passivation layer 280 are removed during RIE.The etching process creates an opening 282 in the passivation layer suchthat a top surface portion of the bond pad 260 is exposed thus allowingconnections such as ball bonds that electrically couple the integratedsystem to external locations to be formed on the bond pad.

In one embodiment, the passivation layer 280 comprises silicon nitrideand is etched using a fluorine based chemistry comprising CF₄, SF₆, orC₄F₈ or a combination of two of more of these gases. Alternatively,other combinations of gases that are suitable for selectively etchingthe passivation layer 280 without damaging the bond pad material mayalso be used. In a preferred embodiment, a high frequency megasonicrinse in de-ionized (DI) water may follow after the completion of thepassivation etch process. The megasonic rinse helps to remove etchby-products such as floating residue and/or polymer that has carbon andfluorine content.

FIG. 4 shows the semiconductor system 200 of FIG. 3 after the maskinglayer 290 has been removed. In one embodiment, the masking layer 290 isphotoresist and it is removed by an oxygen based plasma process.Preferably, the oxygen based plasma process comprises a combination of afirst oxygen containing gas chemistry and a second gas chemistry thataids in etch residue removal. During the RIE process for patterning thepassivation layer 280, etch residues, a by-product of the plasma etchingprocess are formed. These etch residues may include hardened photoresistmaterial, etch residue generated as a result of chemical reactionsoccurring during the plasma etch process, sputtered on materials,re-deposited materials or combinations thereof. A resist strippingprocess that is purely oxygen based does not assist in the removal ofthese etch residues and as such the inclusion of a second gas chemistryfor etch residue removal is preferred. In one embodiment, the etchresidue removal gas chemistry is a fluorine based chemistry such as butnot limited to CF₄ or SF₄.

Following the removal of the masking layer 290, the integrated circuitsystem 200 is subjected to a wet solvent clean process to further removeany remaining etch residue. Commercially available chemical solventssuch as EKC-265, Aleg310 and NE-111 may be used in the wet solvent cleanprocess. Alternatively, other chemical solvents that are capable ofremoving etch residue without damaging the components formed on theintegrated circuit may also be suitable.

In processes where the preceding photoresist strip involves the use offluorine-based gases, the wet clean process also has the added advantageof removing residual fluorine introduced by the use of such gases. Theseresidual traces of fluorine are undesirable as they may react with thebond pad material to bring about bond pad corrosion. For example, if thebond pad is composed of aluminum (Al) or an alloy thereof, the residualtraces of fluorine may cause fluorine-induced bond pad corrosion byreacting with the aluminum to form aluminum fluoride (AlF_(x)) on thesurface of the bond pad. If moisture is present, aluminum fluoride oxide(Al_(x)F_(y)O_(z)) may also be formed.

FIG. 5 shows the integrated circuit system of FIG. 4 after a bond padprotective layer 520 is grown on the exposed top surface portion of thebond pad 260. The bond pad protective layer 520 protects the top surfaceof the bond pad from being corroded. In one embodiment, the bond pad iscomposed of Aluminum alloys (such as Al—Cu, Al—Cu—Si) and the oxidelayer 520 grown is aluminum oxide (Al₂O₃).

A possible reason for bond pad corrosion is due to the formation of anelectrochemical cell when two electrochemically dissimilar metals areplaced in contact. When the electrochemical cell is exposed to water,(for example, when an IC is rinsed in water during processing stepssubsequent to bond pad formation or moisture in the atmosphere), wateracts as an electrolyte which facilitates the occurrence of galvaniccorrosion. During galvanic corrosion, one of the metals acts as an anodethat loses electrons and metal ions while the other metal acts as acathode that gains electrons. Using the example of an aluminum-copperbond pad as an illustration, an electrochemical cell is formed as aresult of the electrochemical differences between aluminum and copper(illustrated in equations (1) and (2)). In particular, aluminum acts asan anode that corrodes preferentially with respect to copper when themetals are exposed to moisture or water because it has a more negativeelectrical potential compared to copper. As illustrated in equations (3)and (4), aluminum loses electrons and aluminum ions by reacting with OH⁻ions in water to form aluminum hydroxide (Al(OH)₃). Copper, on the otherhand, acts as a cathode that gains electrons. In this situation,aluminum corrodes faster than it would compared to when pure aluminum isused while copper, which acts as a cathode, corrodes more slowlycompared to pure copper. However, aluminum is typically mixed withcopper to form an alloy that is used for the bond pad metallizationbecause of the superior qualities that copper has in the prevention ofelectromigration.

Galvanic Corrosion (Al—Cu)Anode: Al³⁺+3e

Al (E ⁰=−1.662 V)   (1)Cathode: Cu²⁺+2e

Cu (E ⁰=+0.337 V)   (2)O₂+2H₂O+4e

4OH⁻ (E ⁰=+0.401 V)   (3)4Al+3O₂+6H₂O→4Al⁺³+12OH⁻→4Al(OH)₃   (4)

By providing a protective layer of aluminum oxide (Al₂O₃) 520 on thesurface of the bond pad, aluminum in the bond pad is shielded fromexposure to moisture or water thus preventing the resultant corrosivereaction (4) from occurring. This is illustrated in equation (5) below.O₂+2H₂O+4e→4OH⁻¹+Al₂O₃/Al→No Reaction to form Al(OH)₃↓  (5)

In one embodiment, the aluminum oxide layer 520 may be formed via aplasma oxidation process involving oxygen or oxygen based gases.Preferably, the plasma oxidation process occurs at a chamber temperatureof at least 200° C. so that moisture trapped at the edges of the bondpad may be removed concurrently with the oxide growth. In alternativeembodiment, the oxide layer 520 may be grown thermally in a hightemperature thermal oxidation process. Preferably, the aluminum oxidelayer 520 formed by either processes is between 50 to 55 angstrom.Alternatively, other values of aluminum oxide layer thickness, which aresufficiently thick to act as a barrier to water while still allowing thesuccessful formation of electrical contacts to the top surface of thebond pad may also be used.

As evident from the above description, the bond pad protective layer 520is only formed after the removal of the photoresist masking layer 290 ina plasma strip process followed by a wet solvent clean process to removeany remaining etch residue or polymer left behind by the passivationlayer 280 RIE. This sequence of steps is critical as the plasma stripand wet clean facilitate the removal of any contaminants such as etchand photoresist residue that may inhibit the growth of a uniform bondpad protective layer. A non-uniform bond pad protective layer 520 mayleave some portions of the bond pad surface less protected and morevulnerable to galvanic corrosion. Furthermore, separating thephotoresist removal and passivation layer formation steps also makes itpossible to introduce a fluorine-based component into the photoresistremoval step. As discussed earlier, a fluorine-based component aids inthe removal of etch residues left behind by preceding RIE steps but cancause bond pad corrosion if the bond pads are not subsequently cleanedto remove fluorine residue. By removing the photoresist in a separatestep and subsequently performing a wet clean to remove fluorine tracesbefore the bond pad protective layer is formed, the risk of fluorineinduced bond pad corrosion can be mitigated.

Turning now to FIG. 6, therein is shown a partial cross sectional viewof an integrated circuit system 600 in accordance with an alternativeembodiment of the present invention. The integrated circuit systemcomprises a substrate 601 including a top metal layer 612 and anoverlying bond pad 620 embedded within an interlayer dielectric 610. Avia 630 contacts a lower surface of the top metal layer 612 while thebond pad is attached to the opposed upper surface of the top metal layer612. The via 630 may be connected to an underlying interconnect orcircuit components (not shown). Although not illustrated in FIG. 6, thesubstrate may also comprises a plurality of active and passive devicesformed below the top metal layer 612 and interconnects linking some ofthe devices to the top metal layer 612. The interconnects comprisemetallic lines and vias embedded in one or more layers of dielectricmaterial. The bond pad is conventional in the art and may comprisemetals such as aluminum, aluminum-copper or alloys thereof.Alternatively, other conductive materials may also be used and the bondpad may also be a laminate structure made up of additional layers ofmaterial such as copper, titanium, titanium nitride or combinationsthereof.

A first composite layer is provided over the interlayer dielectric 610and bond pad 620. In the presently illustrated embodiment, the firstcomposite layer comprises a lower Titanium (Ti) layer 640 proximate thebond pad 620 and interlayer dielectric 610 followed by an intermediateTitanium Nitride (TiN) layer 650 overlying the Ti layer 640 and on theuppermost portion of the first composite layer, a silicon nitride layer660 formed over the TiN layer 650. The silicon nitride layer 660 servesas a passivation layer that protects underlying components of theintegrated system from external contaminants such as moisture andmechanical damage. In alternative embodiments, other materials such asbut not limited to silicon oxynitride and polyimide may also be used asa passivation layer in addition to or as a replacement of siliconoxide/nitride.

An opening 670 is created through the first composite layer so as toallow access to a portion of the bond pad top surface. This is necessaryso that bonding connections such as ball bonds may be subsequentlyformed to the bond pad 620.

As shown in FIG. 6, a bond pad protective layer 680 is formed over thetop surface of bond pad 620 and the edges of the titanium layer 640 andtitanium nitride layer 650 are also covered by a sidewall protectivelayer 690. The protective layers 680 and 690 help to protect the bondpad from corrosion. In one embodiment, the protective layer 680 is anoxide layer grown over the bond pad 620 while the edges of the titaniumand titanium nitride layers 640 and 650 are oxidized to form a sidewallprotective layer 690 composed of titanium oxide and titanium oxynitride.In a preferred embodiment, the bond pad is composed of aluminum copperor alloys thereof and the oxide layer 680 grown over the bond pad isaluminum oxide (Al₂O₃).

A possible reason for bond pad corrosion is due to the formation of anelectrochemical cell when two electrochemically dissimilar metals areplaced in contact. When the electrochemical cell is exposed to water(for example, when an IC is rinsed in water during processing stepssubsequent to bond pad formation or moisture in the atmosphere), wateracts as an electrolyte, which facilitates the occurrence of galvaniccorrosion. During galvanic corrosion, one of the metals acts as an anodethat loses electrons and metal ions while the other metal acts as acathode that gains electrons. With reference to the example shown inFIG. 6, two electrochemical cells may be formed in this embodiment. Thefirst electrochemical cell is the one arising from the use analuminum-copper bond pad 620. As discussed earlier, the electrochemicaldifferences between aluminum and copper (illustrated in equations (1)and (2)) result in the formation of an electrochemical cell wherealuminum corrodes preferentially with respect to copper when the metalsare exposed to moisture or water. In particular, aluminum loseselectrons and aluminum ions by reacting with OH⁻ ions in water to formaluminum hydroxide (illustrated in equations (3) and (4)) while copperacts as a cathode that gains electrons.

The second electrochemical cell is formed between aluminum from the bondpad and titanium from the Ti/TiN layers 640 and 650. When thealuminum-titanium electrochemical cell is exposed to water or moisture,aluminum having a more negative electrical potential acts as an anodethus losing electrons and metal ions while titanium acts as a cathodethat gains electrons. The electrical potential differences betweenaluminum and titanium are shown in equations (5) and (6). Specifically,aluminum corrodes preferentially with respect to titanium by reactingwith OH⁻ ions in water to form aluminum hydroxide (Al(OH)₃) as shown inequations (8) and (9).

Galvanic Corrosion (Al—Ti)Anode: Al³⁺+3e ⁻

Al (E ⁰=−1.662 V)   (5)Cathode: Ti⁴⁺ +e ⁻

Ti³⁺ (E ⁰=−0.040 V)   (6)Ti³⁺ +e ⁻

Ti²⁺ (E ⁰=−0.370 V)   (7)O₂+2H₂O+4e→4OH⁻ (E ⁰=+0.401 V)   (8)4Al+3O₂+6H₂O→4Al⁺³+12OH⁻→4Al(OH)₃↓  (9)

Galvanic corrosion of the bond pad 620 resulting from theelectrochemical cell formed between aluminum and titanium can be avoidedby providing a sidewall protective layer of titanium oxide/titaniumoxynitride 690 at the edges of the titanium/titanium nitride layers 640and 650, respectively, and a bond pad protective layer 680 of aluminumoxide formed over the surface of the bond pad. The bond pad protectivelayer of aluminum oxide 680 protects the aluminum-copper bond pad frombeing exposed to moisture or water and hence the resultant corrosivereaction which follows due to the aluminum-copper electrochemical cell.

In one embodiment, the protective layers 680 and 690 may be formed via aplasma process involving oxygen or oxygen based gases. During the plasmaprocess, the chamber is preferably maintained at a chamber temperatureof 200° C. or more so that moisture trapped at the edges of the bond padmay be removed concurrently with the oxide growth. In alternativeembodiment, the protective layers 680 and 690 may be grown thermally ina high temperature oxidation process. Preferably, the aluminum oxide(Al₂O₃) layer 680 grown over the bond pad is between 50 to 55 angstrom.Alternatively, other values of aluminum oxide layer thickness which aresufficiently thick to act as a barrier to water while still allowing thesuccessful formation of electrical contacts to the top surface of thebond pad may also be used.

Similar to the embodiment described in relation to FIGS. 2-5, the oxidelayers 680 and 690 are only grown after the removal of the photoresistmasking layer for patterning the first composite layer (640, 650 and660) and a wet solvent clean process to remove any remaining etchresidue and polymer left behind by the first composite layer RIE. Thissequence of steps is critical as the plasma strip and wet solvent cleanfacilitate the removal of any contaminants such as etch and photoresistresidue that may inhibit the growth of a uniform aluminum oxide (Al₂O₃)protective layer on the surface of the bondpads. A non-uniform Al oxidelayer may leave some portions of the bond pad surface less protected andmore vulnerable to galvanic corrosion. Furthermore, separating thephotoresist removal and protective layer formation steps also makes itpossible to introduce a fluorine-based component into the photoresistremoval step. As discussed earlier, a fluorine-based component aids inthe removal of etch residues left behind by preceding RIE steps but cancause bond pad corrosion if the bond pads are not subsequently cleanedto remove fluorine residue. By removing the photoresist in a separatestep and subsequently performing a wet solvent clean to remove fluorinetraces before the bond pad protective layer is formed, the risk offluorine induced bond pad corrosion can be mitigated.

The preferred embodiment of the invention is illustrative of theinvention rather than limiting of the invention. It is to be understoodthat revisions and modifications may be made to methods, materials,structures and dimensions of a semiconductor structure while stillproviding a semiconductor that fall within the scope of the includedclaims. All matters hitherto set forth herein or shown in theaccompanying drawings are to be interpreted in an illustrative andnon-limiting sense.

1. A method of fabrication an integrated circuit comprising: providing asubstrate with a bond pad formed thereover, the bondpad having a topsurface for the formation of bonding connections; providing apassivation layer over the bondpad; forming a masking layer over thepassivation layer, the masking layer comprising photoresist; etching thepassivation layer in accordance with the masking layer to form apatterned passivation layer with an opening that exposes a portion ofthe top surface of the bond pad; removing the masking layer to exposethe passivation layer by a plasma strip process, wherein the plasmastrip process comprises a fluorine-based chemistry for removing etchingresidues arising from the step of etching the passivation layer;cleaning the substrate after removing the masking layer by a wet solventclean process to remove etching residues and residual fluorine; andforming a bond pad protective layer on the exposed top surface portionof the bond pad after the wet solvent clean process.
 2. The methodaccording to claim 1, wherein the bond pad protective layer comprises analuminum oxide.
 3. The method according to claim 1, wherein the maskinglayer comprises photoresist.
 4. The method according to claim 1, whereinthe plasma strip process comprises an oxygen containing gas chemistry.5. The method according to claim 1, wherein the wet solvent cleanprocess removes polymer residues.
 6. The method according to claim 1,wherein at least one of the chemical solvents EKC-265, Aleg310 or NE-111is used in the wet solvent clean process.
 7. The method according toclaim 1, wherein the bond pad comprises an aluminum copper based alloy.8. The method according to claim 1, wherein the bond pad protectivelayer is composed of aluminum oxide.
 9. The method in claim 1 whereinthe bond pad protective layer is formed by an oxidation process.
 10. Themethod in claim 9 wherein the oxidation is a plasma oxidation process(POP) performed at a temperature of at least about 200° C.
 11. A methodof fabrication an integrated circuit comprising: providing a substratewith a bond pad formed thereover; providing a passivation layer over thebondpad; forming a masking layer over the passivation layer, the maskinglayer comprising photoresist; etching the passivation layer with amasking layer to form an opening that exposes a portion of the topsurface of the bond pad; removing the masking layer to expose thepassivation layer by a plasma strip process, wherein the plasma stripprocess comprises a fluorine-based chemistry for removing etchingresidues from etching the passivation layer; and cleaning the substrateafter removing the masking layer with a wet solvent clean process toremove etching residues and residual fluorine.
 12. The method of claim11 comprises forming a bond pad protective layer on the exposed topsurface portion of the bond pad after the wet clean process.
 13. Themethod of claim 12 wherein forming the bond pad protective layercomprises a plasma oxidation process (POP).
 14. The method of claim 13wherein the plasma oxidation process (POP) is performed at a temperatureof at least about 200° C.
 15. The method of claim 12 wherein the bondpad protective layer comprises aluminum oxide.
 16. The method of claim12 wherein forming the bond pad protective layer comprises an oxidationprocess.
 17. The method of claim 12 wherein the bond pad protectivelayer comprises oxide.
 18. The method of claim 11 wherein the maskinglayer comprises photoreist.
 19. The method of claim 11, wherein the wetclean solvent process comprises at least one of the chemical solventsEKC-265, Aleg310 or NE-111.
 20. The method of claim 11 wherein the setclean solvent process removes polymer residue.
 21. A method offabrication an integrated circuit comprising: providing a substrate witha bond pad formed thereover, the bondpad having a top surface for theformation of bonding connections; providing a passivation layer over thebondpad; forming a masking layer over the passivation layer, the maskinglayer comprising photoresist; etching the passivation layer inaccordance with the masking layer to form a patterned passivation layerwith an opening that exposes a portion of the top surface of the bondpad; and removing the masking layer to expose the passivation layer by aplasma strip process, wherein the plasma strip process comprises afluorine-based chemistry for removing etching residues arising from thestep of etching the passivation layer.